1. Field of the Invention
The present invention relates, to a data latch circuit such as inverter circuit composed of semiconductor elements and having simplified latching function.
2. Prior Art
Recently, various types of input inverter circuits are proposed and used in the field of IC memory. In order to stably and properly operate the IC memory, the input inverter circuits are required to have features such as a narrow non-sensitive region with respect to the determination of input level, a latching function for an external input voltage, a simplified structure of the input inverter circuitry and a small electric current consumption. The following description is directed to the inverter circuit composed of metal oxide semiconductor transistors (hereinafter, referred to as "MOST") which are typical of insulated-gate type field effect transistors, and particularly N-channel MOSTs are used as examples. However, the inverter circuit may be composed of P-channel MOSTs or bipolar transistors.
FIG. 1 shows an example of principal structure of the conventional input inverter circuit. The illustrated input inverter circuit is comprised of an enhancement type metal oxide semiconductor transistor (hereinafter, referred to as "EMOST") J1 for sampling an external input voltage V.sub.IN, an EMOST J2 for sampling a reference voltage V.sub.REF, an EMOST J3 connected at its gate terminal to the source terminal of the EMOST J1, an EMOST J4 connected at its gate terminal to the source terminal of the EMOST J2, a flip-flop differential voltage amplifier circuit 1 for comparing the external input voltage V.sub.IN and the reference voltage V.sub.REF to each other and amplifying the voltage difference therebetween, and a flip-flop current-amplifier circuit 5 for current-amplifying the output from the flip-flop differential voltage amplifier circuit 1. In this circuit, the reference voltage V.sub.REF is outputted from a reference voltage generating circuit formed in a portion of semiconductor substrate other than the area on which the input inverter circuit is formed. The input inverter circuit 1 compares the external input voltage V.sub.IN with the reference voltage V.sub.REF as a reference level to process the external input voltage.
FIG. 2 is a detailed circuit diagram of the conventional input inverter circuit shown in FIG. 2. This circuit exemplifies an input inverter circuit used in a MOS dynamic RAM of the conventional 5 V-single-power source type IC. As shown in FIG. 2, a plurality of EMOSTs J5-J12 constitute the flip-flop differential voltage amplifier circuit 1, and a plurality of EMOSTs J13-J24 constitute the flip-flop current-amplifier circuit 5.
Next, operation of the conventional input inverter circuit will be explained with reference to FIG. 2. In the initial stage, since a pre-charge signal .phi..sub.P is set to a high voltage level (hereinafter, referred to as "high level") sufficiently exceeding a threshold voltage level V.sub.T of the EMOSTs, the EMOSTs J9, J10, J21, J22, J23 and J24, all receptive of the pre-charge signal .phi..sub.P as their gate input signal, are activated so that nodes N3 and N4 are held at the high level, and nodes N5 and N6 as well as output signals .phi..sub.02 and .phi..sub.02 are held at a low voltage level (hereinafter, referred to as "low level") lower than the threshold voltage level V.sub.T. Thereafter, the pre-charge signal .phi..sub.P is turned to the low level. On the other hand, when a latching signal .phi..sub.L is turned from the high level to the low level, the EMOSTs J1 and J2 are turned off so that the external input voltage V.sub.IN and the reference voltage V.sub.REF are latched at nodes N1 and N2, respectively. When a first activating signal .phi..sub.1 is turned from the low level to the high level, the potentials of nodes No and No are boosted. At this time, a voltage difference is produced between the node No and node No by means of the EMOST J3 connected at its input gate terminal to the node N1 at which the external input voltage V.sub.IN is latched and by means of the EMOST J4 connected at its input gate terminal to the node N2 at which the reference voltage V.sub.REF is latched. A pair of EMOSTs J7 and J8, which constitute a flip-flop, are operated by the voltage difference between the node No and Node No so that one of the nodes N4 and N3 is turned to the low level by means of the EMOST J12 connected at its input gate terminal to the node No and the EMOST J11 connected at its input gate terminal to the node No, and therefore one of the EMOST J6 connected at its input gate terminal to the node 4 and the EMOST J5 connected at its input gate terminal to the node N3 is deactivated (hereinafter, this condition is referred to as "OFF"). Subsequently, when a second activating signal .phi..sub.2 is turned from the low level to the high level, one of the nodes N5 and N6 is held at the high level through activated one of the EMOST J13 connected at its input gate terminal to the node No and the EMOST J14 connected at its input gate terminal to the node No. One of the EMOST J17 connected at its input gate terminal to the node N5 and the EMOST J18 connected at its input gate terminal to the node N6 is activated, and a current-amplified signal is outputted at one of the nodal outputs .phi..sub.02 and .phi..sub.02 . At this stage, the nodal output .phi..sub.02 has the same phase as that of the external input voltage V.sub.IN, and the nodal output .phi..sub.02 has the opposite phase to that of the external input voltage V.sub.IN.
However, in the above-described conventional circuitry structure, when the external input voltage V.sub.IN is at the high level, the node No is held at the high level. In this state, since the EMOST J4 receptive of the reference voltage V.sub.REF as its gate input signal is always held at the activated state, a current flows from the node No held at the high level to the ground (hereinafter, referred to as "GND") to thereby increase the current consumption. In addition, since the EMOST J4 is always held in the activated state, the flip-flop differential voltage amplifier circuit of the conventional circuitry cannot hold information represented by the external input voltage V.sub.IN. Consequently, an additional flip-flop is needed in the flip-flop differential voltage amplifier circuit to hold the information of external input voltage V.sub.IN, so that the flip-flop differential voltage amplifier circuit is complicated and requires a lot of EMOSTs. Further, in the conventional circuitry, during the activation of flip-flop differential voltage amplifier circuit, if the external input voltage V.sub.IN is fluctuated, the EMOSTs J1 and J2 and the latching signal .phi..sub.L to be fed to the input gate terminals thereof are needed in order to properly carry out the different-al voltage amplification.